diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index 962ec2b..acac21e 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -18,6 +18,7 @@
 
 config TARGET_B4420QDS
 	bool "Support B4420QDS"
+	select ARCH_B4420
 	select SUPPORT_SPL
 	select PHYS_64BIT
 
@@ -257,6 +258,9 @@
 
 endchoice
 
+config ARCH_B4420
+	bool
+
 config ARCH_B4860
 	bool
 
diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile
index 87d8b18..c19c3e7 100644
--- a/arch/powerpc/cpu/mpc85xx/Makefile
+++ b/arch/powerpc/cpu/mpc85xx/Makefile
@@ -47,7 +47,7 @@
 obj-$(CONFIG_PPC_T4240) += t4240_ids.o
 obj-$(CONFIG_PPC_T4160) += t4240_ids.o
 obj-$(CONFIG_PPC_T4080) += t4240_ids.o
-obj-$(CONFIG_PPC_B4420) += b4860_ids.o
+obj-$(CONFIG_ARCH_B4420) += b4860_ids.o
 obj-$(CONFIG_ARCH_B4860) += b4860_ids.o
 obj-$(CONFIG_PPC_T1040) += t1040_ids.o
 obj-$(CONFIG_PPC_T1042)	+= t1040_ids.o
@@ -89,7 +89,7 @@
 obj-$(CONFIG_PPC_T4240) += t4240_serdes.o
 obj-$(CONFIG_PPC_T4160) += t4240_serdes.o
 obj-$(CONFIG_PPC_T4080) += t4240_serdes.o
-obj-$(CONFIG_PPC_B4420) += b4860_serdes.o
+obj-$(CONFIG_ARCH_B4420) += b4860_serdes.o
 obj-$(CONFIG_ARCH_B4860) += b4860_serdes.o
 obj-$(CONFIG_ARCH_BSC9132) += bsc9132_serdes.o
 obj-$(CONFIG_PPC_T1040) += t1040_serdes.o
diff --git a/arch/powerpc/cpu/mpc85xx/b4860_ids.c b/arch/powerpc/cpu/mpc85xx/b4860_ids.c
index 85eba0b..4ceb6f5 100644
--- a/arch/powerpc/cpu/mpc85xx/b4860_ids.c
+++ b/arch/powerpc/cpu/mpc85xx/b4860_ids.c
@@ -62,7 +62,7 @@
 	SET_DMA_LIODN(1, "fsl,elo3-dma", 147),
 	SET_DMA_LIODN(2, "fsl,elo3-dma", 227),
 
-#ifndef CONFIG_PPC_B4420
+#ifndef CONFIG_ARCH_B4420
 	SET_GUTS_LIODN("fsl,rapidio-delta", 199, rio1liodnr, 0),
 	SET_GUTS_LIODN(NULL, 200, rio2liodnr, 0),
 	SET_GUTS_LIODN(NULL, 201, rio1maintliodnr, 0),
@@ -81,7 +81,7 @@
 	SET_FMAN_RX_1G_LIODN(1, 3, 91),
 	SET_FMAN_RX_1G_LIODN(1, 4, 92),
 	SET_FMAN_RX_1G_LIODN(1, 5, 93),
-#ifndef CONFIG_PPC_B4420
+#ifndef CONFIG_ARCH_B4420
 	SET_FMAN_RX_10G_LIODN(1, 0, 94),
 	SET_FMAN_RX_10G_LIODN(1, 1, 95),
 #endif
diff --git a/arch/powerpc/cpu/mpc85xx/b4860_serdes.c b/arch/powerpc/cpu/mpc85xx/b4860_serdes.c
index 64db7a7..a5709dd 100644
--- a/arch/powerpc/cpu/mpc85xx/b4860_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/b4860_serdes.c
@@ -180,7 +180,7 @@
 };
 #endif
 
-#ifdef CONFIG_PPC_B4420
+#ifdef CONFIG_ARCH_B4420
 static struct serdes_config serdes1_cfg_tbl[] = {
 	{0x0D, {NONE, NONE, CPRI6, CPRI5,
 		CPRI4, CPRI3, NONE, NONE} },
diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
index 2d3517b..a392414 100644
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -202,7 +202,7 @@
 	}
 #endif
 
-#if defined(CONFIG_ARCH_B4860) || defined(CONFIG_PPC_B4420) || \
+#if defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420) || \
 	defined(CONFIG_PPC_T2080) || defined(CONFIG_PPC_T2081)
 #define FM1_CLK_SEL	0xe0000000
 #define FM1_CLK_SHIFT	29
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index 5b6dcad..d705e5c 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -611,7 +611,7 @@
 #define CONFIG_SYS_FSL_SFP_VER_3_0
 #define CONFIG_SYS_FSL_PCI_VER_3_X
 
-#elif defined(CONFIG_ARCH_B4860) || defined(CONFIG_PPC_B4420)
+#elif defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420)
 #define CONFIG_E6500
 #define CONFIG_SYS_PPC64		/* 64-bit core */
 #define CONFIG_FSL_CORENET		/* Freescale CoreNet platform */
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index dc3369a..fdf7080 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1770,7 +1770,7 @@
 #define FSL_CORENET2_RCWSR4_SRDS4_PRTCL		0x000000f8
 #define FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT	3
 #define FSL_CORENET_RCWSR6_BOOT_LOC	0x0f800000
-#elif defined(CONFIG_ARCH_B4860) || defined(CONFIG_PPC_B4420)
+#elif defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420)
 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL	0xfe000000
 #define FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT	25
 #define FSL_CORENET2_RCWSR4_SRDS2_PRTCL	0x00ff0000
@@ -2883,8 +2883,8 @@
 #define CONFIG_SYS_MPC85xx_TDM_OFFSET		0x185000
 #define CONFIG_SYS_MPC85xx_QE_OFFSET		0x140000
 #define CONFIG_SYS_FSL_CORENET_RMAN_OFFSET	0x1e0000
-#if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && !defined(CONFIG_ARCH_B4860)\
-	&& !defined(CONFIG_PPC_B4420)
+#if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && !defined(CONFIG_ARCH_B4860) && \
+	!defined(CONFIG_ARCH_B4420)
 #define CONFIG_SYS_MPC85xx_PCIE1_OFFSET		0x240000
 #define CONFIG_SYS_MPC85xx_PCIE2_OFFSET		0x250000
 #define CONFIG_SYS_MPC85xx_PCIE3_OFFSET		0x260000